Abstract: Advanced Digital multipliers are the most critical arithmetic functional units. The general execution of these systems depends on the throughput of the multiplier. While negative bias temperature instability (NBTI) effects on logic gates are of major concern for the reliability of digital circuits, they become even more critical when considering the components for which even minimal parametric variations affect the lifetime of the overall circuit. In the mean time, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (V gs=-Vdd), increasing the threshold voltage of the pMOS transistor, and decresing multiplier speed. A similar phenomenon, positive bias temperature instability, happens when an nMOS transistor is under positive bias. Both effects or impacts reduce transistor speed, and in the long term, the system may fail because of timing infringement. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier can give higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect.

Keywords: Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), reliable multiplier, variable latency.